1. Field of the Invention
The present invention relates to stacked (i.e. three-dimensional) integrated circuits (ICs) (also called chips herein), and in particular to processing the designs of two chips simultaneously to achieve global optimum solutions using a standard single-chip electronic design automation (EDA) tool.
2. Related Art
In three-dimensional (3D) IC technology, multiple dies can be stacked vertically with inter-chip connections using through-silicon-vias (TSVs) and micro-bumps (MBs). The TSV is a standard 3D object that forms electrical interconnection between a front metal 1 layer and a back metal 1 layer of a chip. Thus, the TSV can be used to carry a signal (e.g. power or other signals) from one side of a chip to its other side. Note that the back metal 1 layer has no transistors, unlike the front metal 1 layer. Note further that the TSVs are on the order of 5-10 microns wide, which based on a standard cell size of 1 micron, can be considered a valuable chip resource.
The MB is a spherical piece of metal on the top-most metal layer or on the bottom-most back metal layer of the chip. MBs are used to form the electronic contacts between two neighboring chips in a stack. Note that although a MB is described below, other embodiments of the two-chip co-design technique may use other types of “bumps”, which could be larger or smaller than MBs. Therefore, the term MB, as used herein, can be broadly described as any bump.
The locations of TSVs are typically formed in an array, which spacing may vary based on the design. In current state of the art designs, thousands of TSVs may be needed. In one embodiment, the TSVs of the chip may be placed every 50 microns. Although theoretically the MBs may be placed directly above the TSVs, in actual practice, the MBs are placed adjacent the TSVs, with the connections (i.e. wires) therebetween being part of the RDL (re-distribution layer). In general, once a design is designated, the TSVs and MBs can be considered a “given” with minimal or no user discretion allowed for TSV and MB placement.
The net assignment flow for 3D IC designs currently includes a single-chip net assignment step, which assigns and connects TSVs to MBs to form intra-chip paths. An inter-chip net assignment step then assigns and connects inter-chip signals to these paths while attempting to minimize total wire length.
Notably, the inter-chip net assignment is a two-chip co-design and co-optimization problem. After the connection on one chip is determined, the connection on the other chip can be derived. The objective of inter-chip net assignment is to optimize the total wire length of all the inter-chip nets between the two chips.
Thus, the problem is, given two chips and the inter-chip paths between them, finding an assignment of inter-chip signals to inter-chip paths while minimizing the total weighted wire length. Optimally, wires on signal routing layers and wires on RDL routing layers should be weighted differently in the wire length calculation.